;*****************************************************************************
; 68HC12 REGISTERS
;****************************************************************************
COPCTL: equ $0016 ;COP Register [CME,FCME,FCM,FCOP,DISR,CR2,CR1,CR0]
SC0BDH: equ $00C0 ;SCI 0 Baud Rate Reg H [BTST,BSPL,BRLD,SBR12,SBE11,SBR10,SBR9,SBR8]
SC0BDL: equ $00C1 ;SCI 0 Baud Rate Reg L [SBR7,SBR6,SBR5,SBR4,SBR3,SBR2,SBR1,SBR0]
SC0CR1: equ $00C2 ;SCI 0 Control Reg 1 [LOOPS,WOMS,RSRC,M,WAKE,ILT,PE,PT]
SC0CR2: equ $00C3 ;SCI 0 Control Reg 2 [TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK]
SC0SR1: equ $00C4 ;SCI 0 Status Reg 1 [TDRE,TC,RDRF,IDLE,OR,NF,FE,PF]
SC0DRL: equ $00C7 ;SCI Data Register Low [R7/T7,R6/T6,R5/T5,R4/T4,R3/T3,R2/T2,R1/T1,R0/T0]
PPAGE: equ $0035 ;Program Page Register [PPA21,PPA20,PPA19,PPA18,PPA17,PPA16,PPA15,PPA14]
SC1BDH: equ $00C8 ;SCI 1 Baud Rate Reg H [BTST,BSPL,BRLD,SBR12,SBE11,SBR10,SBR9,SBR8] A
SC1BDL: equ $00C9 ;SCI 1 Baud Rate Reg L [SBR7,SBR6,SBR5,SBR4,SBR3,SBR2,SBR1,SBR0]
SC1CR1: equ $00CA ;SCI 1 Control Reg 1 [LOOPS,WOMS,RSRC,M,WAKE,ILT,PE,PT]
SC1CR2: equ $00CB ;SCI 1 Control Reg 2 [TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK]
SC1SR1: equ $00CC ;SCI 1 Status Reg 1 [TDRE,TC,RDRF,IDLE,OR,NF,FE,PF]
SC1SR2: equ $00CD ;SCI 1 Status Reg 2 [0,0,0,0,0,0,0,RAF]
SC1DRL: equ $00CF ;SCI Data Register Low [R7/T7,R6/T6,R5/T5,R4/T4,R3/T3,R2/T2,R1/T1,R0/T0]
CSCTL0: equ $003C ;Chip-Sel Control Reg 0 [0,CSP1E,CSPOE,CSDE,CS3E,CS2E,CS1E,CS0E]
CSCTL1: equ $003D ;Chip-Sel Control Reg 1 [0,CSP1FL,CSPA21,CSDHF,CS3EP,0,0,0]
CSSTR0: equ $003E ;Chip-Sel Stretch Reg 0 [O,O,SRP1A,SRP1B,SRPOA,SRPOB,STRDA,STRDB]
CSSTR1: equ $003F ;Chip-Sel Stretch Reg 1 [STR3A,STR3B,STR2A,STR2B,STR1A,STR1B,STR0A,STROB]
MXAR: equ $0038 ;Memory Exp Assig Reg [0,0,A21E,A20E,A19E,A18E,Acooooppp17E,A16E]
WINDEF: equ $0037 ;winmitte Definition Reg [DWEN,PWEN,EWEN,0,0,0,0,0]
PORTE: equ $0008 ;Port E Register [PE7,PE6,PE5,PE4,PE3,PE2,PE1,PE0]
DDRE: equ $0009 ;Port E Data Dir Reg [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,0,0]
PEAR: equ $000A ;Port E Assig Reg [ARSIE,CDLTE,PIPOE,NECLK,LSTRE,RDWE,0,0]
PORTG: equ $0031 ;Port G Register [0,0,PG5,PG4,PG3,PG2,PG1,PG0]
DDRG: equ $0033 ;Port G Data Dir Reg [0,0,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
PORTH: equ $0024 ;Port H Register [PH7,PH7,PH5,PH4,PH3,PH2,PH1,PH0]
DDRH: equ $0025 ;Port H Data Dir Reg [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
SP0CR1: equ $00D0 ;SPI 0 Contr Register 1 [SPIE,SPE,SWOM,MSTR,CPOL,CPHA,SS0E,LSBF]
SP0CR2: equ $00D1 ;SPI 0 Contr Register 2 [0,0,0,0,PUPS,RDS,0,SPC0]
SP0BR: equ $00D2 ;SPI Baud Rate Register [0,0,0,0,0,SPR2,SPR1,SPR0]
SP0SR: equ $00D3 ;SPI Status Register [SPIF,WCOL,0,MODF,0,0,0,0]
SP0DR: equ $00D5 ;SPI Data Register [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
PORTS: equ $00D6 ;Port S Data Register [PS7,PS6,PS5,PS4,PS3,PS2,PS1,PS0]
DDRS: equ $00D7 ;Port S Data Dir Register[DDRS7,DDRS6,DDRS5,DDRS4,DDRS3,DDRS2,DDRS1,DDRS0]
;************************************
ATDCTL0: equ $0066 ;Reserved [0,0,0,0,0,0,0,0]
ATDCTL2: equ $0062 ;ATD Control Register 2 [ADPU,AFFC,AWAI,0,0,0,ASCIE,ASCIF]
ATDCTL3: equ $0063 ;ATD Control Register 3 [0,0,0,0,0,0,FRZ1,FRZ0]
ATDCTL4: equ $0064 ;ATD Control Register 4 [0,SMP1,SMP0,PRS4,PRS3,PRS2,PRS1,PRS0]
ATDCTL5: equ $0065 ;ATD Control Register 5 [0,S8CM,SCAN,MULT,CD,CC,CB,CA]
ATDSTAT0: equ $0066 ;ATD Status Register [SCF,0,0,0,0,OC2,OC1,OC0]
ATDSTAT1: equ $0067 ;ATD Status Register [CCF7,CCF6,CCF5,CCF4,CCF3,CCF2,CCF1,CCF0]
PORTAD: equ $006F ;Port AD Data input Reg [PAD7,PAD6,PAD5,PAD4,PAD3,PAD2,PAD1,PAD0]
ADR0H: equ $0070 ;ADC Result Register [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
ADR1H: equ $0072 ;ADC Result Register [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
ADR2H: equ $0074 ;ADC Result Register [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
ADR3H: equ $0076 ;ADC Result Register [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
ADR4H: equ $0078 ;ADC Result Register [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
ADR5H: equ $007A ;ADC Result Register [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
ADR6H: equ $007C ;ADC Result Register [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
ADR7H: equ $007E ;ADC Result Register [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
PORTJ: equ $0028 ;Port J Register [PJ7,PJ6,PJ5,PJ4,PJ3,PJ2,PJ1,PJ0]
DDRJ: equ $0029 ;Port J Data Dir Reg [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
TIOS: equ $0080 ;Timer IC/OC Select [IOS7,IOS6,IOS5,IOS4,IOS3,IOS2,IOS1,IOS0]
CFORC: equ $0081 ;Timer Compare Force Reg [FOC7,FOC6,FOC5,FOC4,FOC3,FOC2,FOC1,FOC0]
OC7M: equ $0082 ;Output Compare 7 Mask [OC7M7,OC7M6,OC7M5,OC7M4,OC7M3,OC7M2,OC7M1,OC7M0]
OC7D: equ $0083 ;Output Compare 7 Data [OC7D7,OC7D6,OC7D5,OC7D4,OC7D3,OC7D2,OC7D1,OC7D0]
TCNT: equ $0084 ;Timer Count Register [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
TSCR: equ $0086 ;Timer System Control [TEN,TSWAI,TSBCK,TFFCA,0,0,0,0]
TQCR: equ $0087 ;Reserved [0,0,0,0,0,0,0,0]
TCTL1: equ $0088 ;Timer Control Reg 1 [OM7,OL7,OM6,OL6,OM5,OL5,OM4,OL4]
TCTL2: equ $0089 ;Timer Control Reg 2 [OM3,OL3,OM2,OL2,OM1,OL1,OM0,OL0]
TCTL3: equ $008A ;Timer Control Reg 3 [EDG7B,EDG7A,EDG6B,EDG6A,EDG5B,EDG5A,EDG4B,EDG4A]
TCTL4: equ $008B ;Timer Control Reg 4 [EDG3B,EDG3A,EDG2B,EDG2A,EDG1B,EDG1A,EDG0B,EDG0A]
TMSK1: equ $008C ;Timer Interrupt Mask 1 [C71,C6I,C5I,C4I,C3I,C2I,C1I,C01]
TMSK2: equ $008D ;Timer Interrupt Mask 2 [TOI,0,TPU,TDRB,TCRE,PR2,PR1,PR0]
TFLG1: equ $008E ;Timer Interrupt Flag 1 [C7F,C6F,C5F,C4F,C3F,C2F,C1F,C0F]
TFLG2: equ $008F ;Timer Interrupt Flag 2 [TOF,0,0,0,0,0,0,0]
TC0: equ $0090 ;Timer IC/OC Register 0 [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
TIC0: equ $0090
TC1: equ $0092 ;Timer IC/OC Register 1 [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
TC2: equ $0094 ;Timer IC/OC Register 2 [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
TIC2: equ $0094
TC3: equ $0096 ;Timer IC/OC Register 3 [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
TC4: equ $0098 ;Timer IC/OC Register 4 [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
TIC4: equ $0098
TC5: equ $009A ;Timer IC/OC Register 5 [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
TC6: equ $009C ;Timer IC/OC Register 6 [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
TIC6: equ $009C
TC7: equ $009E ;Timer IC/OC Register 7 [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
PACTL: equ $00A0 ;Puls Accu Control Reg [0,PAEN,PAMOD,PEDGE,CLK1,CLK0,PAOVI,PAI]
PAFLG: equ $00A1 ;Puls Accu Flag Register [0,0,0,0,0,0,PAOVF,PAIF]
PACNT: equ $00A2 ;16-Bit Puls Accu Count [BIT15,BIT14,BIT13,BIT12,BIT11,BIT10,BIT9,BIT8]
TIMTST: equ $00AD ;Timer Test Register [0,0,0,0,0,0,TCBYP,PCBYP]
PORTT: equ $00AE ;Port T Register [PT7,PT6,PT5,PT4,PT3,PT2,PT1,PT0]
DDRT: equ $00AF ;Port T Data Dir Reg [BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0]
RTICTL: equ $0014 ;RTI Control Register [RTIE,RSWAI,RSBCK,0,RTBYP,RTR2,RTR1,RTR0]
; RTR2 RTR1 RTR0 4 MHz 8 MHz T [ms]
; 0 0 0 OFF OFF
; 0 0 1 2.048 1.024
; 0 1 0 4.096 2.048
; 0 1 1 8.196 4.096
; 1 0 0 16.384 8.196
; 1 0 1 32.768 16.384
; 1 1 0 65.536 32.768
; 1 1 1 131.720 65.536
RTIFLG: equ $0015 ;RTI Flag Register [RTIF,0,0,0,0,0,0,0]
